1. Field Of The Invention
This invention relates to digital communications systems, and more particularly to a method and apparatus for recovering clock information from a data stream.
2. Background Art
Data processing systems commonly employ serial data communication paths. Serial data is typically transferred at relatively slow rates so that it is inefficient for a central processor to maintain real time control over data transfers. Accordingly, it is common practice to include a serial communications controller in a data processing system architecture. Such devices are readily available from various manufacturers. One such device is the Z8030/Z8530 serial communications controller (SCC) distributed by Zilog, Inc. of Campbell, Calif.
The Zilog SCC is a dual-channel, multi-protocol data communications peripheral device intended for use with eight and sixteen-bit microprocessors. Each channel of this device contains an internal digital phase-locked loop (DPLL) for recovery of clock information from a data stream with NRZI or FM encoding. The internal DPLL is driven by a clock having a frequency that is nominally 32 (NRZI encoding) or 16 (FM encoding) times the data rate. The DPLL uses this clock, along with the data stream to construct a receive clock for the data. This clock can then be used as the SCC receive clock, the transmit clock, or both. The device may also operate with an external DPLL, and one of the objects of the present invention is to provide an external DPLL suitable for use with a SCC of the type thus described.